Since the development of the integrated circuit (IC), the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, these improvements in integration density have come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the area occupied by the integrated components is essentially on the surface of the semiconductor wafer. Various techniques have been developed to attempt to incorporate extra dimensionality into IC structures.
One technique is referred to as a two and a half dimensional (2.5D) structure. These structures typically have interposers having a die stacked on the interposer. Interposers have been used to redistribute ball contact areas from that of the chip to a larger area of the interposer. Further, interposers have allowed for a package that includes multiple chips.
Other techniques stack chips in a three dimensional (3D) structure. This allows for greater functionality with a reduced footprint of the structure.